“A 56Gb/s PAM4 Wireline Transceiver using a 32-way Time-Interleaved SAR ADC in 16nm FinFET”
A lecture by Yohan Frans (Xilinx)
Friday, 11 November 2016, 11:45 AM–12:45 PM
The emergence of Internet of Things (IOT) and cloud computing has triggered a rapid increase in bandwidth demand in data centers and telecommunication infrastructures, prompting the industry to propose a new electrical interface standard capable of operating up to 56Gb/s per-lane over a legacy channel built for lower data-rate. This presentation discusses the design of a 56Gb/s ADCbased PAM4 transceiver with a moderate target BER (e.g. 1e-6 to 1e-8) over legacy channels to be used with Forward Error Correction (FEC). Architecture and circuit solutions to address transmitter and receiver design challenges will be covered, as well as measurement results from a test-chip implemented in 16nm FinFET.
Yohan Frans received B.S. degree in electrical engineering from Bandung Institute of Technology, Indonesia in 1995 and the M.S. degree in electrical engineering from Stanford University, California in 2001. From 2001 to 2012, he was with Rambus Inc. where he worked on high-performance and low-power serial links and memory interfaces as circuit design engineer, circuit architect, and design manager. Since 2012 he has been with Xilinx Inc, San Jose, CA. He is currently leading design teams as Senior Engineering Director in Xilinx Serdes Technology Group, developing high-speed wireline transceivers for advanced FPGA. His current interests include high-speed mixed-signal circuit design, serial link architecture, transmitter/receiver design, PLL/DLL, memory interfaces, and low-power circuit architectures.
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