Talk: R&D for 3D-Power in Japan

Professor Satoshi Matsumoto

Kyushu Institute of Technology, Fukuoka, Japan

Co-sponsored by the UK and Ireland Chapter of the IEEE Solid-State Circuits Society and Connect

Monday, 14 March 2016, 3pm-4pm, Tyndall National Institute (Block B, Ground Floor, Room B.O.17)

Note: Those from outside the Tyndall National Insitute must register in advance by emailing

Cutting edge R&D for Power SoC started in the mid-1990s in Japan. Professor Matsumoto’s research group began work on 3D Power SoC. This presentation traces the history of R&D for 3D Power SoC in Japan and covers current research also, including 3D stacking technology, heat extraction, circuits and control technology.

Satoshi Matsumoto received a B.S., M.S., and Dr. Eng degree in applied chemistry from Waseda University, Tokyo, Japan in 1982, 1984 and 1996 respectively. In 1984 he joined NTT (Nippon Telegraph and Telephone Corporation) LSI Laboratories where he worked on the research and development of SOI Bi-CMOS devices, power ICs, analog high frequency devices and circuits and energy harvesting systems. In 2010 he moved to Kyushu Institute of Technology as a professor. His research interests include 3D integrated circuits and energy harvesting technology.

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